As memory bit cells of ICs get smaller and/or denser, the likelihood of a Single Event Upset (“SEU”) impacting more than one memory bit cell at a time increases. Adding parity bits for resolving data corruption using an Error-Correcting Code (ECC) may address data corruption at least to a limited extent. One way of addressing larger amounts of data corruption, in view of increased density of memory bit cells, is to add more parity bits. Using additional parity bits, however, can adversely affect the bandwidth of memories at a time when increased memory bandwidth is highly valued.